Digital systems are used for a range of different purposes when it comes to processing and calculation of data, such as in control systems, communication systems, and measuring systems. Digital circuits use discreet signals, which are usually binary, i.e. only two values are used. The advantage with this is that the reliability with regard to errors is good, ensuring that the circuits are accurate.
Analog systems use analog signals, which vary continously within a range. Thus analog systems are more vulnerable to errors.
Digital systems normally comprise a central processing unit (CPU) that executes arithmetic functions (for instance addition, subtraction, and division), and logic functions (for instance AND, OR, NAND, NOR, and NOT). The arithmetic and logic functions are executed by a number of logic gates, or circuit elements, which are interconnected, and form a network with multiple logic depths. The logic circuit elements normally include one or more inputs, and an output. The number of inputs are described as the “fan-in” of the circuit element. Usually, AND denotes the logic function AND with two inputs, whereas AND3 denotes the same function with three inputs. The notation “′” denotes inversion.
When designing circuits, a range of considerations must be taken into account, particularly with regard to the requirements of the application. The circuit elements include, for example, different types of transistors, capacitors, and resistors, which are selected with regard to these requirements.
CMOS-transistors are devices with four nodes or electrodes, namely the source, drain, gate, and well. In this context, two types of such transistors exist, p-channel MOSFET transistors and n-channel MOSFET transistors. In most applications of such transistors, the well is connected to the source.
Within the development of processor units, there is a large focus on speed. As the speed of the processor units increase, so does the power requirement and the operating temperature. Processing units are used, for example, in laptop computers, where the power consumption should not be too great in relation to the battery capacity.
In a range of other applications, the power consumption is far more important than the speed. This applies to space technology, units for biological implants, neuromorph electronics, and nano technology, for instance. In neuromorph electronics, such as electric circuits that model or simulate neural networks, both digital and analog signals are often used in the inputs and the outputs of the circuits.
It is known to reduce the operating voltage in electric circuits, so that the transistors operate in what is called subthreshold, or weak inversion. From the paper “Robust Ultra-Low Power Sub-threshold DTMOS Logic”, Soeleman, H., Roy, K. and Paul, B., ISLPED 2000, Rapallo, Italy, it is known that operation in this area results in a significant reduction in power consumption. However, a consequence is that the circuit becomes slower, compared to the classic operation area.
Threshold logic uses discreet signals with two or more values. For instance, ternary logic uses three values on the output, whereas quaternary logic uses four. Threshold logic can also have multiple discreet levels on the input signals, while the output signal is binary, i.e. logic 0 or 1.
The following formula yields the sign f of the weighted sum of a series of inputs x1 . . . xn:
                              f          ⁡                      (                                          x                1                            ,              …              ⁢                                                          ,                              x                n                                      )                          =                  sgn          ⁡                      (                                                            ∑                                      i                    =                    1                                    n                                ⁢                                                      ω                    i                                    ⁢                                      x                    i                                                              -              θ                        )                                              [        1        ]            where ωi denotes the weight of the input xi, θ denotes the threshold value, and n denotes the number of inputs, or fan-in. This is known from Beiu et al., mentioned below.
It is known that circuit elements, which use threshold logic, may reduce the number of transistors and the amount of wiring. This reduces the chip area, which results in a reduction in the production costs.
The paper “VLSI Implementations of Threshold Logic—A Comprehensive Survey”, Beiu, Valeriu et al, IEEE Transactions on neural networks, vol. 14, No. 5. September 2003 provides an historical overview of the technical developments in the field of threshold logic. Here, U.S. Pat. No. 3,715,603 is mentioned, which describes a majority-minority circuit element, which is achieved with six transistors. This will function as a logic NOR2 or a logic NAND2 circuit element. The drawback with this circuit is that an inverter is required to amplify the signal before the output.
Object
The main object of the present invention is to provide a logic circuit element with very low power consumption. The circuit element shall contain very few transistors and very little wiring.
An additional object is that the function of the circuit element shall be reconfigurable in real time.
The Invention
The present invention is indicated in the characterizing part of claim 1. An additional aspect of the invention is indicated in the characterizing part of claim 5. Further embodiments appear from the dependent claims.
In the following example of embodiment, MOS transistors are used. However, the invention should not be restricted to the use of MOS transistors. Transistor units in general may also be used. With transistor unit is meant any device having the possibility of controlling the current and/or voltage characteristics between nodes of the unit, by applying voltage and/or current to an additional node. In the circuit element according to the invention, the transistor units have at least four nodes. Such a unit can be a MOS-transistor with the nodes DRAIN, SOURCE, GATE, and WELL.
FIG. 1 illustrates an embodiment of the invention. Here, the circuit element comprises N=3 pairs of transistors, but N can vary from N=2 upwards. There is one pair of transistors per input terminal, which means that N also denotes the number of input terminals. If a digital output signal shall be used, the delays in the circuit element will limit the number of input terminals.
Each pair of transistors comprises an NMOS transistor MN, and a PMOS transistor MP. The first pair of transistors comprises the NMOS transistor MN, and the PMOS transistor MP1, the second pair comprises the NMOS transistor MN2 and the PMOS transistor MP2, whereas the third pair of transistors comprises the NMOS transistor MN3 and the PMOS transistor MP3. In this embodiment, the transistors are devices with four nodes or electrodes, namely source, drain, gate, and well. The drain node of the NMOS transistor MN is connected to the drain node of the PMOS transistor MP. Furthermore, the drain terminal of the first pair of transistors is connected to the drain terminal of the second pair of transistors, which in turn is connected to the drain terminal of the third pair of transistors.
The source node of the NMOS transistor is connected to a lower voltage level VSS, which is typically earth or 0 V. The source node of the PMOS transistor is connected to an upper voltage level VDD. The supply voltage in many of the standard CMOS integrated circuits of today is 3.3 V. The voltage level VDD will therefore typically be less than 1 V, so that the transistors operate in subthreshold, or weak inversion.
The circuit element further comprises N=3 input terminals X1, X2 and X3. The input terminal X1 is connected both to the gate node of the PMOS transistor MP1, and to the gate node of the NMOS transistor MN1, whereas the input terminal X2 is connected both to the gate node of the PMOS transistor MP2, and to the gate node of the NMOS transistor MN2, and the input terminal X3 is likewise connected both to the gate node of the PMOS transistor MP3, and to the gate node of the NMOS transistor MN3.
Furthermore, the circuit element comprises an output terminal CN, which is connected to the drain node of the PMOS transistor MP3 and to the drain terminal of the NMOS transistor MN3. Off course, the output terminal CN may be connected to any of the drain nodes of the transistor pairs.
The circuit element also comprises a control terminal BN connected to the well nodes of the NMOS transistors MN1, MN2, and MN3, and a control terminal BP, connected to the well nodes of the PMOS transistors MP1, MP2, and MP3.
This circuit element has a range of applications, of which some will be described in further detail by means of the following examples: